Small Linux Device - Development board PXA 255

Small Linux Device
Development board PXA 255

This PXA 255 board is intended for running embedded network applications. The PXA 255 board is optimised for the development of highly e.cient Internet devices, and for network infrastructure applications.

The PXA 255 board is based on the new Intel XScale architecture. Intel XScale processor family increases e_ciency and decreases processor power consumption. The Intel XScale micro architecture is based on the Intel Strong ARM technology.

Intel Strong ARM and Intel XScale are compatible with the ARM architecture, which in turn guarantees the compatibility of software solutions. The PXA 255 board includes Intel XScale processor, SDRAM and Intel StrataFlash memory, 2 Ethernet controllers,3 serial interfaces and 1 stereo audio output.

Product name	CPU	Flash	SDRAM	Audio	Ethernet
SLD PXA 255 Basic	200 MHz	8 MB	32 MB	optional	2x 10 Mbit
SLD PXA 255 PRO	400 MHz	32 MB	64 MB	optional	2x 10 Mbit
SLD PXA 255 Server	200 MHz	16 MB	64 MB	optional	2x 10 Mbit

Hardware Specification

CPU	Intel XScale PXA 255
Clock	200/400 MHz
Memory	Flash 8..32 MB
	SDRAM 32..64 MB
On-Board Peripherals :	1x asynchronous serial port, RS232 level
	1x asynchronous serial port, 3.3-5V level (RTS/CTS hadshaking only)
	1x synchrnous serial port, 3.3-5V level, support SSPC, SSP and SPI protocols
	2x Ethernet 10BASE-T port (chip CS8900a)
	1x JTAG
Audio (optional)	AD1885 AC'97 audio codec
Power Supply :	7-12V DC / max 5W
Dimension :	100 x 107 mm
Temperatures :	Commercial 0°C až +70°C
	Industrial: -40°C až +85°C (without audio chip)

Software Specification

The PXA 255 board is delivered with preinstalled boot loader and Linux kernel. This firmware support direct application loading and running via Ethernet.

This firmware can be changed via JTAG interface, development boot loader or through mtd device (on the running kernel).

The sources codes for development are on the „CD Development tools for PXA 255 Board“.

Boot loader :	proprietary for production Armboot for developing
Kernel :	2.4.19 with patches for ARM, Xscale and proprietary hardware

Hardware

2.1 Board Layout

The upper layer of board provide console port, reset button, three GPIO LED, two RJ-45 10BASE-T ports, four Ethernet LEDs , power connector and power LED.

1 console port

2 reset button

3 GPIO LEDs

4 10BASE-T (eth1)

5 10BASE-T (eth0)

6 Ethernet LEDs

7 power connectors

8 power LED

The bottom layer of board provide serial port (3-5V), flash lock jumper and JTAG interface.

1 JTAG

2 SP0

3 SP1

4 SSP

5 Audio

Connectors and jumpers

Power

7,5V DC (connector: 5.5x2.1mm, centre positive)

Console RS232

asynchronus serial port (V.28 voltage levels, FFUART)

Pin	Description	Pin	Description
1	SP0 DCD	6	SP0 DSR
2	SP0 RXD	7	SP0 RTS
3	SP0 TXD	8	SP0 CTS
4	SP0 DTR	9	SP0 RI
5	GND

SP0 RS232

asynchronus serial port (V.28 voltage level, FFUART)

Pin	Description	Pin	Description
1	SP0 DCD	6	SP0 DSR
2	SP0 RXD	7	SP0 RTS
3	SP0 TXD	8	SP0 CTS
4	SP0 DTR	9	SP0 RI
5	GND

SP1 3-5V

asynchronus serial port (BTUART), 5V tolerant I/O pins accept 5V,3.3V

Pin	Description	Pin	Description
1	VCC5	2	VCC3.3
3	SP1 BT CTS	4	GND
5	SP1 BT RTS	6	GND
7	SP1 BT RXD	8	GND
9	SP1 BT TXD	10	GND

SSP

synchronous serial port, 5V tolerant I/O pins accept 5V,3.3V

Pin	Description	Pin	Description
1	VCC5	2	VCC3.3
3	SSP FRM	4	GND
5	SSP CLK	6	GND
7	SSP TXD	8	GND
9	SSP RXD	10	GND

JTAG interface

JTAG allows burning into the flash memory or debugging the processor.

Pin	Description	Pin	Description
1	VCC5	2	VCC3.3
3	SSP FRM	4	GND
5	SSP CLK	6	GND
7	SSP TXD	8	GND
9	SSP RXD	10	GND

Audio (optional)

Connector AUDIO contains outputs of the Audio Codec.

Pin	Description	Pin	Description
1	LINE IN L	2	LINE OUT L
3	LINE IN R	4	LINE OUT R
5	AGND	6	MONO OUT
7	MIC1 IN	8	HP OUT L
9	MIC1 REF	10	HP OUT R

Ethernet 1OBASE-T RJ45 connector

Pin	Description	Pin	Description
1-2	TXD	3-6	RXD

Jumper

JP331 FLASH ERASE ENABLE (with jumper)
JP331 FLASH ERASE DISABLE (without jumper)

LED

D221 connected to PXA 255 GPIO3
D222 connected to PXA 255 GPIO4
D223 connected to PXA 255 GPIO5
D224 power LED
D411 Ethernet 0 LINK
D412 Ethernet 0 ACTIVE
D711 Ethernet 1 LINK
D712 Ethernet 1 ACTIVE

Switch

RESET reset board

2.3 Description of on-board devices

2.3.1 SDRAM memory 64 MB

The board uses two 256Mbit SDRAM devices organised as one 32-Bit Bank. They support 100MHz operation.

2.3.2 Flash memory 16MB

The board uses two Intel 28F640J3 flash chips organised as one 32-Bit Bank.

2.3.3 Address map

The board used standard address map with the following modification:

Pin		Description
CS0	(0-0x03FF.FFFF)	flash memory
CS1	(0x0400.0000-0x07FF.FFFF)	unused
CS2	(0x0800.0000-0x0BFF.FFFF)	Ethernet 1
CS3	(0x0C00.0000-0x0FFF.FFFF)	Ethernet 2
CS4	(0x1000.0000-0x13FF.FFFF)	unused
CS5	(0x1400.0000-0x17FF.FFFF)	unused

2.3.4 Ethernet controller

The Cirrius Logic CS8900a is used to provide 10Mbit Ethernet interface via twisted-pair.

2.3.5 AC’97 stereo audio codec AD1885 (optional)

The PXA 255 implements a standart ac’97 Codec interface. An AD1885 AC’97 codec (or equivalent) allows this interface to transmit and receive analog audio data. The AD1885 is located at AC’97 input 0.

The AD1885 also integrates a Headphone Output Apmplifier and a Microphone Input Amplifier for ease of use.

2.3.6 GPIO Port Pin Assignments

GPIO (General purpose I/O pins) pin can be individually programmed as an output or an input. The following table describes the GPIO pins used by this board.

Pin	Description
0-2	unused
3-5	USER LEDs D221,D222,D223
6-12	unused
13	Ethernet reset
14	Ethernet 1 interrupt
15-18	unused
19	Ethernet 2 interrupt
20	free pin for hardware configuration by connecting the R261(High) or R262(Low) Resistor through 4.7k
21-22	unused
23-27	SSP
28-31	AC'97
32	free pin for hardware configuration by connecting the R261(High) or R262(Low) Resistor through 4.7k
33	unused
34-41	UART 0
42-45	UART 1
46-47	IRDA
48-77	unused
78	Ethernet 1 chipselect
79	Ethernet 2 chipselect
80	unused

2.3.7 PXA 255 serial ports

The PXA 255 has three asynchronous serial ports (FFUART,BTUART and STUART) and one synchronous serial port (SSPC). The FFUART supports full handshaking, while the BTUART supports RTS/CTS only.

Only two UARTs of the processor are routed to the connectors: FFUART and STUART. The FFUART is shared by the SP0 (10-pin heder) and RS232 Connectors (DB-9 male) at V.28 power levels. The SP1 connector(10-pin header) connects to the BTUART and adopts for power levels of 3.3-5V.

The synchronous serial port (SSP) supports three protocols: National Semiconductor s Microwire, Texas Instruments Synchronous Serial Protocol, and Motorola’s Serial Peripheral Interface. This port is routed to a 10-Pin Header SSP.

2.3.8 PXA 255 Initialization

It is necessary to initialize certain internal registers before correct operation can begin.

WARNING: Change to some register values may result in damaging behaviour of the hardware.

GPIO port control registers

These registers control the direction of the various GPIO port pins. The following table describes the control bits and their values that are required, to place the GPIO pins in the correct mode based upon the uPC usage for each GPIO.

GPIOSR0 (0x40E0.0018) = 0xFFFF.FFFF
GPIOSR1 (0x40E0.001C) = 0xFFFF.FFFF
GPIOSR2 (0x40E0.0020) = 0xFFFF.FFFF
GPCR0 (0x40E0.0024) = 0x0802.2080
GPCR1 (0x40E0.0028) = 0x0000.0000
GPCR2 (0x40E0.002C) = 0x0000.0000
GPDR0 (0x40E0.000C) = 0xCB82.A8D8
GPDR1 (0x40E0.0010) = 0xFCFF.AB83
GPDR2 (0x40E0.0014) = 0x0001.FFFF
GPIOAFR0L (0x40E0.0054) = 0x8000.0000
GPIOAFR0U (0x40E0.0058) = 0xA51A.8010
GPIOAFR1L (0x40E0.005C) = 0x5999A.9558
GPIOAFR1U (0x40E0.0060) = 0xAAA5.AAAA
GPIOAFR2L (0x40E0.0064) = 0x0000.5000
GPIOAFR2U (0x40E0.0068) = 0x0000.0002

Static memory controller configuration registers

The Static Chip Selects are setup to conform to the requirements of the various I/O devices. All timing is done using MCLK, which is 99.5MHz (cca 10nsec per clock). If lower frequency operation is desired, these values will need to be adjustned appropriately. The folloqing table lists recommended values for each of the static memory control registers.

MSC0 (0x4800.0008) = 0x2EF1.5AF0
MSC1 (0x4800.000C) = 0x3FF4.3FF4
MSC2 (0x4800.0010) = 0x0000.0000

SDRAM controller configuration registers

Attached to the PXA 255 SDRAM Controller are two banks of two each, 8Mbit x 16 (or optionally 16Mbit x 16) SDRAM devices. In order for these devices to operate properly several SDRAM control registers must be set correctly. All timing is done using MCLK, which is 99.5MHz, or 10nsec per clock. If lower frequency operation is desired, these values will need to be adjusted appropriately. The following table lists recommended values.

MDCNFG (0x4800.0000) = 0x09A9.09A9
MDREFR (0x4800.0004) = 0x038F.F030
MDMRS (0x4800.0040) = 0x0022.0022

2.4 Switch and LEDs (optional)

The Board can accommodate the Reset Switch. The Switch may be connected if desired. The power LED indicates that power is applied to the board.

Three user LEDs are driven from the GPTIO processor pins. A low level turns the LEDs on. It is necessary to connect the LED’s to the following 330R Resistors (D221 and R221, D222 and R222, D223 and R223).

Two ethernet LEDs are used to provide status indication for each Ethernet. It is necessary to connect corresponding Resistors (D411 and R411, D412 and R412, D711 and R711, D712 and R712 ).

2.5 Flash erase jumper

Jumper JP331 must be inserted in case you want to erase anything from the flash memory.

2.6 Power

A standard 2.1mm DC jack is used to provide power the board. The center of jack is positiv. It is recommended to power the board by stabilised source 7.5V-12V.

Software & Development tools

Programming flash via JTAG

The programming through JTAG interface is suitable for primary software burning (e.g. production or developer boot loader) into flash memory.

There are several software for programming FLASH through JTAG. We are tested Jflashmm from Intel (for Widows) and jtag from from OpenWinCE project (linux). Jflashmm is fast than jtag, but jtag is more reliable. We will use jtag in this guide. You need for compiling jtag install two source code from OpenWinCE: include and jtag-0.4. Use this command for instalation:

tar -xzv include.tar.gz
cd includeXX
configure
make
make install
tar -xzv jtagXX
cd jtag
configure
make
make install

Then connect JTAG to the board and to the parallel port on computer. Run software for programming through JTAG by command jtag.

Follow these steps for JTAG software initialisation (cable is connected to parallel port at address 0x378):

1.	cable parallel 0x378 DLC5	you have to determine type of JTAG cable
2.	detect	detect type of CPU
3.	detectflash	detect type of flash memory

You can use prepared script cable by command jtag cable. For reading/ writing file from/to flash memory use this commands:

readmem 0x0 0x20000 armboot.bin

to read data with length 0x2000 bytes from flash memory to file boot loader.bin

flashmem 0x0 armboot.bin

to write data from file armboot.bin to address 0x0

For help use command help. For exiting from jatg use command quit.

Product name	Description	1 pcs
SLD PC Board Basic	200 MHz CPU, 8 MB FLASH, 32 MB SDRAM, AUDIO	7.930,-
SLD PC Board SERVER	200 MHz CPU, 16 MB FLASH, 64 MB SDRAM, AUDIO	8.784,-
SLD PC Board PRO	400 MHz, 32 MB Flash, 64 MB SDRAM AUDIO	10.126,-

Sources & download

Download Order Form

Download specifications SLD PC Board - sld_pcboard.pdf
Download datasheets (Česky) - PXA 255_datasheet_cz_v003.pdf
Download datasheets (English) - PXA 255_guide.pdf

Primary source about ARM architekture: www.arm.com.
Arm Reference Manual: www.arm.com/ARMARM.
Information about PXA 255 firmware and hardware you can find on: developer.intel.com
Sources and manuals for gcc, gdb, glib+ and binary utilities : www.gnu.org.
Kernel souces and patches are on the page: www.arm.linux.org.uk.
Information about PXA 255 firmware and hardware: developer.voipac.com

Other Information about SLD devices, starter kits atd. http://www.HW-group.com/